1. Field of the Invention
The present invention relates to a structure of a bonding pad portion of a gate electrode of a microwave power field effect transistor (FET).
2. Description of the Prior Art
A prior art arrangement of electrodes of a microwave power FET is illustrated in FIGS. 1, 2, 3 and 4. This FET is made of GaAs and is used for high frequency amplification or oscillation in such a range as 4 GHz to 18 GHz. On the surface of the semiconductor chip SC of the FET illustrated in FIG. 1, there are provided a source electrode 2 having finger portions 201, 202, 203, 204, 205 and 206 and a source contact portion 21, a drain electrode 3 having finger portions 301, 302, 303, 304 and 305 and a drain contact portion 31 and a gate electrode 4 having portions 401, 402, 403, 404, 405, 406, 407, 408, 409 and 410 and a gate bonding pad portion 41'.
The cross sections taken along the lines II--II, III--III and IV--IV of FIG. 1 are illustrated in FIGS. 2, 3 and 4, respectively. The cross-sectional structure of the FET of FIG. 1 comprises a semi-insulating monocrystalline substrate 11, a semi-insulating buffer layer 12, an n type active layer 13 and an insulation layer 14 of silicon dioxide. The end of the insulation layer is designated by 14a.
The interdigital structure of the electrodes illustrated in FIG. 1 is adopted in order to increase the width of the gate electrode and simultaneously decrease the resistance of the gate electrode of the FET.
An example of such a prior art structure of an FET is disclosed in a publication "GaAs Microwave Power FET" by M. Fukuta et al, in IEEE Transactions on Electron Devices, Vol. ED-23, No. 4, April 1976.
In the structure of the FET illustrated in FIG. 1, the source electrode is usually connected to a ground bus through an L-shaped sheet made of conductive material such as gold, and the connection to said L-shaped sheet is formed by a gold-tin solder. This is because the above described FET is usually used in a common source configuration and in such a case it is necessary to reduce the source inductance by connecting a large area of the source electrode to the ground bus through the shortest distance.
In the above described structure in which the source electrode is connected to the ground bus, it is also necessary to reduce the distance between the end portion 211 of the source electrode, where the soldering to the ground bus is effected, and the active portion 1 of the FET. However, in the prior art structure illustrated in FIG. 1 it is difficult to reduce said distance between the end portion 211 and the active portion 1 below 250 .mu.m because of the existence of the gate bonding pad 41'. Thus, in the prior art structure it is difficult to reduce the source inductance, and accordingly it is difficult to obtain a large valve of the maximum available gain of the FET. For example, only a maximum available gain of 1 dB in 8 GHz is obtained by a prior art high power FET having a gate width of 20 mm. Although it is desired to reduce the inductance of the bus from the active source area to ground, especially in a large gate width FET in order to increase maximum available gain of the FET, it has been difficult to get the inductance smaller than 40 pH.